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MT48LC4M16A2 1 Meg x 16 x 4 Banks. Features. PC100- and PC133- compliant. Fully synchronous; all signals registered on positive edge of system clock. 4.1.4 EMIF SDRAM Refresh Period for C6201B to MT48LC4M16A2 . 63 Appendix A Code Example for C6201B to Micron MT48LC4M16A2 -10. 73. Apr 1, 2010 A [4]. A [3]. A [2]. A [1]. D [15:0]. DCTL. High. DQ [15:0]. 1 Mwords 16 bits 4 banks. MT48LC4M16A2 . SDRAM. 22 . BA1. BA0. A11. A10. A9. ADSP-BF535 EZ-KIT Lite . Evaluation System Manual. Revision 3.1, April 2006. Part Number. 85-000603-01. Analog Devices, Inc. One Technology Way. SDRAM = 2 x Micron MT48LC4M16A2 or same for 32 bit wide SDRAM bank of 16M bytes. SDRAM controller is dedicated to this interface. Optional upgrade to